Amiram Jibly is a System Engineer in the Network ASIC design team at Intel, has been with Intel in the last 7 years and is experienced in package and board design for high speed systems and signal integrity. His current work focuses on 100 Gb Ethernet validation systems and SI. His experience includes Si/Pi simulations for 25 and 56 Gb. products and accurate measurement based modeling of passive interconnects. He received his BSc Degree from the Jerusalem College of Engineering in 2012.
